# Set associative cache calculations

I found the following problem:

Given the following specifications for an external cache memory: four-way associative set; line size of two 16-bit words; capable of accommodating a total of 4K 32-bit words from main memory; used with a 16-bit processor that emits 24-bit addresses. Design the cache structure with all the relevant information and show how it interprets the processor addresses.

I tried to solve it in the following way:

• 4 lines per game
• Word size of main memory: $$32$$ bits $$= 2 ^ 4$$
• Word size of the cache: $$16$$ bits $$= 2 ^ 2$$
• Size of main memory: $$4 times 2 ^ {10} = 2 ^ {12}$$ words of $$32$$ bits $$= 2 ^ {13}$$ words of $$16$$ bits
• The cache must adapt to the main memory. So the size of the cache = size of the main memory $$= 2 ^ {13}$$ words of $$16$$ bits
• Line size $$=$$ two 16-bit words $$rightarrow$$ Word displacement $$= 1$$ bits
• Associative set of four directions. $$rightarrow 4 = 2 ^ 2$$ lines per set
• Set size $$= 2 ^ 2 text {lines} times 2 text {words per line} = 2 ^ 3$$ words of 16 bits in size
• Number of sets $$= 2 ^ {13} / 2 ^ 3 = 2 ^ {10}$$
• Set the index size $$= 10$$ bits
• Label size = Size of the address of 24 bits $$–$$ 10 bit set index $$–$$ 1 bit word shift = 13 bit

Doubts

1. I am surprised how it is said that the 16-bit processor generates 24-bit addresses. it's possible? I never encountered such problem.
2. How can the cache and main memory have different word sizes? Here, the word size of the cache is 16 bits and the word size of the main memory is 32 bits.
3. Taking into account the unusual scenarios (assumptions I made) explained in points 1 and 2 above, am I correct with the previous calculations?
4. The answer only gives a diagram (without explanation) that says 1 bit per word, 1 bit per byte address and 12 bits per label. So, am I wrong?